This invention relates to displays and to systems for maintaining synchronization in displays.
As an introduction to the problems solved by the present invention, consider the conventional flat panel matrix display having a row-column array of picture elements (pixels), each pixel at the intersection of a row and a column. Display in such pixels is conventionally accomplished by a display cell matrix aligned with the pixel matrix so that each display cell is addressed as a member of one row and one column. In an active matrix display, where each display cell includes at least one switch, each display cell is addressed for enabling display when it receives a column pointer signal and a row pointer signal. Many thousands of such pointer signals are needed to address a moderate size matrix of, for example, one million pixels arranged in one thousand rows and one thousand columns. Without integrated circuit packaging techniques, reliable displays having so many interconnections are not economically feasible.
One type of matrix display includes the field emission display wherein the matrix of display cells, circuits for generating the column and row pointer signals, and all the interconnecting conductors are formed on an integrated circuit substrate. Although it would be highly desirable to form video signal processing circuits on the same substrate, further integration of such support circuitry on the substrate has been frustrated by the excessive amount of substrate surface area occupied by conventional addressing circuits, and the excessive power consumed by such circuits.
Conventional video signals are sophisticated, requiring considerable circuitry for deriving color and intensity information for each pixel. In the conventional video signal, row and column addressing information must be derived from the video signal by synchronizing higher frequency clock signals with the video signal, by counting pulses, by detecting pulse frequency, and by detecting pulse duty cycle. Using conventional circuitry, these functions cannot be economically formed on the integrated circuit substrate with other display circuitry because conventional circuitry requires considerable substrate surface area, consumes excessive power, and is so complex that overall reliability goals cannot be economically met.
Without economical integrated circuit displays, systems designs will be limited to use of bulky, unreliable cathode ray tube displays, slow, dim liquid crystal displays, and expensive electroluminescent displays. Such limitations on systems designs will effectively prohibit introduction of new, portable, long life, reliable, and sophisticated industrial and consumer products in wide ranging fields including, for example, such fields as instrumentation, communications, entertainment, photography, and information processing.
In view of the problems described above and related problems that consequently become apparent to those skilled in the applicable arts, the need remains in matrix display products for improved matrix displays and methods for synchronizing such displays with an input signal.
The present invention is a circuit and method for producing a walking one pattern in a shift register. The circuit comprises a shift register and a NOR gate. The NOR gate output is connected to the data input of the shift register, and the data output of each of said shift register stages is connected to a respective one of the NOR gate inputs.
The invention is particularly useful in an electro-optic display having a matix of display cells arranged in rows and columns. The output of each stage of the shift register preferably is associated with one column of the display and controls a transfer gate circuit, which can be a single transistor, so as to couple the video signal to that column of display cells when the output of that shift register stage is a logical one.
Accordingly, a display in one embodiment of the present invention is responsive to an input signal. The input signal includes a recurring pulse, a first value at a first time, and a second value at a second time. The second time being after the first time by a predetermined duration. The display includes a first pixel, a second pixel, and a shift circuit. The shift circuit determines the predetermined duration by synchronizing display operation with the recurring pulse. The shift circuit also identifies the first pixel for displaying responsive to the first value and identifies the second pixel for displaying responsive to the second value.
According to a first aspect of such an embodiment, the shift circuit performs multiple functions. By performing multiple functions, several benefits inure including: over all display circuit complexity is reduced, less surface area on the integrated circuit substrate is used for addressing and video signal processing functions, reliability and manufacturing yields are improved, and power and heat consumption are reduced.
A field emission display, according to another embodiment of the present invention, receives a synchronizing signal and includes: a target and an integrated circuit. The integrated circuit includes a grid, a field emission tip, and a phase locked loop. The target, located adjacent to the integrated circuit, includes a phosphorescent substance. The grid defines a matrix of pixels on the target. The field emission tip responds to a pointer signal for displaying by emission from the tip through the grid and toward a pixel of the matrix, enabling the pixel to phosphoresce. The phase locked loop includes an oscillator, a shift circuit, and a comparator. The oscillator provides a clock signal at a period responsive to an error signal. The shift circuit shifts in response to the clock signal, and provides the pointer signal and an overflow signal. The comparator provides the error signal by comparing in response to the synchronizing signal and the overflow signal.
According to an aspect of such an embodiment of the present invention, the shifting circuit provides both the overflow signal for synchronization of the phase locked loop and the pointer signal for enabling phosphorescence in the addressed pixel. The need for additional synchronizing circuitry, such as a counter for dividing the oscillator signal period, is eliminated with benefits as already recited above.
The present invention may be practiced according to a method in one embodiment for maintaining synchronization in a display, the display being responsive to a video signal that includes a first, a second, and a third plurality of periods. Each period of the first, the second, and the third plurality is characterized by a duration. The video signal during each period of the first plurality is characterized by a respective pulse and a respective value. Each respective value during each period of the first plurality is within a range of magnitudes. The second plurality of periods follows after the first plurality of periods. The video signal during each period of the second plurality is characterized by a respective pulse and a respective value. Each respective value during each period of the second plurality is characterized by a first magnitude outside the range. The third plurality of periods follows after the second plurality of periods. The video signal during each period of the third plurality is characterized by a respective pulse and a respective value. Each respective value during each period of the third plurality is a second magnitude outside the range.
The method includes the steps of (1) determining for each period a first respective time when the respective pulse is expected to begin and identifying a second respective time; (2) determining a third time when the second plurality of periods is expected to begin; (3) establishing the start time; and (4) repeating the three foregoing steps, thereby maintaining synchronization.
According to a first aspect of such a method, by detecting the respective value in each period, vertical synchronization is reliably achieved. Circuitry for performing such a method is simpler, uses less substrate surface area, and consumes less power.
A frame buffer includes a timing control for scanning a matrixed array in yet another embodiment of the present invention. The frame buffer is similar to the display embodiments, except a matrix of memory cells is employed in place of the matrix of display cells. Each memory cell stores samples taken from the input signal at a predetermined time after a recurring synchronization signal is received. The timing control includes means for reading the memory cells and means for outputting values read from memory.
According to a first aspect of such a frame buffer, by decreasing the size and complexity of the frame buffer as in the present invention over conventional frame buffers, a larger number of samples are stored in one semiconductor frame buffer circuit. Such a frame buffer finds application in video, communication, and measurement systems wherein each frame comprises an increased amount of data, for example, for a larger frame or for increased resolution and accuracy.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.